
IDT70914S
High-Speed 36K (4K x 9) Synchronous Dual-Port Static RAM
Functional Description
The IDT70914 provides a true synchronous Dual-Port Static RAM
interface. Registered inputs provide very short set-up and hold times on
address, data, and all critical control inputs. All internal registers are clocked
on the rising edge of the clock signal. An asynchronous output enable is
provided to ease asynchronous bus interfacing.
The internal write pulse width is dependent on the LOW to HIGH
Truth Table I: Read/Write Control (1)
Military, Industrial and Commercial Temperature Ranges
transitions of the clock signal allowing the shortest possible realized cycle
times. Clock enable inputs are provided to stall the operation of the address
and data input registers without introducing clock skew for very fast
interleaved memory applications.
A HIGH on the CE input for one clock cycle will power down the
internal circuitry to reduce static power consumption.
Synchronous
(3)
Inputs
Asynchronous
Outputs
CLK
↑
↑
↑
↑
CE
H
L
L
X
R/ W
X
L
H
X
OE
X
X
L
H
I/O 0-8
High-Z
DATA IN
DATA OUT
High-Z
Mode
Deselected, Power-Down
Selected and Write Enabled
Read Selected and Data Output Enable Read
Outputs Disabled
3490 tbl 09
Truth Table II: Clock Enable Function Table (1)
Inputs
Register Inputs
Register Outputs (4)
Mode
Load "1"
Load "0"
Hold (do nothing)
CLK (3)
↑
↑
↑
X
CLKEN (2)
L
L
H
H
ADDR
H
L
X
X
DATAIN
H
L
X
X
ADDR
H
L
NC
NC
DATAOUT
H
L
NC
NC
NOTES:
3490 tbl 10
1. 'H' = HIGH voltage level steady state, 'h' = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition, 'L' = LOW voltage level steady state 'l' = LOW
voltage level one set-up time prior to the LOW-to-HIGH clock transition, 'X' = Don't care, 'NC' = No change
2. CLKEN = V IL must be clocked in during Power-Up.
3. Control signals are initialted and terminated on the rising edge of the CLK, depending on their input level. When R/ W and CE are LOW, a write cycle is initiated on
the LOW-to-HIGH transition of the CLK. Termination of a write cycle is done on the next LOW-to-HIGH transistion of the CLK.
4. The register outputs are internal signals from the register inputs being clocked in or disabled by CLKEN .
10
6.42